Comparators are commonly employed for threshold detection applications where the output of the comparator changes state depending on whether a variable input voltage is above or below a reference voltage. For example, a comparator can be used as a zero crossing detector to provide a logic level digital output signal based on an AC input voltage developed by a magnetic variable reluctance speed sensor.
In applications where electrical noise is superimposed on an input signal, the comparator may change states based on the noise content of the input signal when the input voltage approaches the switch point of the comparator. To desensitize the comparator to such noise, the comparator circuit is designed with a hysteresis characteristic which effectively increases or decreases the reference voltage, depending on the output state of the comparator.
A conventional technique for providing hysteresis with resistive feedback in a discrete circuit mechanization is depicted in FIG. 2. The comparator 10 is connected between a regulated source voltage +V and ground potential, as shown. The input voltage Vin is applied via line 12 to the inverting (-) comparator input, the reference voltage Vref is applied via line 14 and resistor R1 to the non-inverting (+) comparator input, and the output signal Vout is developed on line 16. The resistors R1, R2 and R3 form a divider network that differentially alters the threshold voltage Vth at the (+) input of the comparator, depending on the state of the output signal Vout. When the output signal Vout is high (+V), a feedback current through resistors R2 and R3 increases the threshold voltage Vth. When the output signal Vout is low (ground potential), the resistor R3 is effectively connected in parallel with resistor R2, thereby lowering the threshold voltage Vth.
The theoretical effect of the above-described feedback is graphically depicted in FIG. 1, which depicts the output signal Vout as a function of the input voltage Vin. As Vin is increased from a relatively low value, the output signal Vout remains high (+V) until the input voltage exceeds the reference voltage Vref by a hysteresis voltage Vhyst. At such point, as designated by (Vref+Vhyst), the output signal Vout transitions to its low state (0). As the input voltage is subsequently reduced, the output signal Vout remains low until the input voltage falls below the reference voltage Vref by the hysteresis voltage Vhyst. At such point, as designated by (Vref-Vhyst), the output signal Vout transitions to its high state (+V).
Although commonly used in nondemanding applications, the above-described circuit cannot meet precise performance specifications in applications requiring a ground reference, such as in zero crossing detection. Unless a bi-polar voltage supply is used, the designer is faced with a trade-off between asymmetric hysteresis and overly restrictive signal range limitations.
In a MOS comparator, hysteresis may be achieved with the circuit depicted in FIG. 3. The basic comparator is defined by a current source transistor Qs feeding a pair of coupled differential transistors Q5, Q6, each of which is connected in series with a load transistor Q1, Q4. The current path dimensions (width W and length L) of the differential transistors Q5 and Q6 are matched, as are the current path dimensions of the load transistors Q1 and Q4.
The input voltage Vin is applied to the gate of differential transistor Q5 and the reference voltage Vref is applied to the gate of differential transistor Q6. A bias voltage Vbias is applied to the gate of source transistor Qs to maintain the source current Is at a constant value, and the source current Is is variably divided between the first and second differential transistors Q5 and Q6 depending on the relative magnitudes of Vin and Vref. An output stage comprising the transistors Q7-Q10 is connected to the first and second comparator legs at junctions 20 and 22 as shown, developing an inverted output voltage Vout.sup.* on line 24.
When the input voltage Vin is much less than the reference voltage Vref, the preferred path for the source current Is is through transistors Q5 and Q1, turning on output stage transistors Q9, Q7 and Q8. The output stage transistor Q10 is off, or nearly so, due to the lack of current flow in the second comparator leg, and Vout.sup.* is substantially equal to +V. This condition prevails until the input voltage Vin increases beyond the reference voltage Vref, whereupon the preferred path for the source current Is is through the transistors Q6 and Q4, turning on output stage transistor Q10. The output stage transistors Q7, Q8 and Q9 are off, or nearly so, due to the lack of current flow in the first comparator leg, and Vout.sup.* is maintained substantially at ground potential.
Hysteresis in the switch point of the MOS comparator circuit is provided by the additional MOS transistors Q2 and Q3, referred to herein as hysteresis transistors. The current path dimensions of the hysteresis transistors Q2 and Q3 are matched, and higher in overall transconductance than the matched load transistors Q1 and Q4. Algebraically, this may be expressed as: EQU W1/L1&lt;W2/L2, W1/L1=W4/L4 and W2/L2=W3/L3
The hysteresis transistors Q2 and Q3 are cross-coupled between the first and second comparator legs, and effectively shift the switch point of the comparator above and below the reference voltage Vref to achieve a hysteresis characteristic as illustrated by the idealized trace of FIG. 1.
When the input voltage Vin is much less than the reference voltage Vref, and the preferred path for the source current Is is through transistors Q5 and Q1, the hysteresis transistor Q2 is also gated on. In this condition, transistor Q2 attempts to conduct current in proportion to the current I1 through transistor Q1. This current, referred to as the hysteresis current I2(h), can be expressed as: EQU I2(h)=I1.multidot.[(W2/L2)/(W1/L1)]
where I1 is the current through load transistor Q1, W2 and L2 represent the current path width and length dimensions of hysteresis transistor Q2, and W1 and L1 represent the current path width and length dimensions of load transistor Q1. When Vin is significantly less than Vref, the current I2 through hysteresis transistor Q2 is much less than the hysteresis current I2(h).
As the input voltage increases, some of the source current Is flows through transistors Q6 and Q2, but the comparator only switches state when such current increases beyond the hysteresis current I2(h). Due to the current shunting operation of hysteresis transistor Q2--taking current away from load transistor Q4--the input voltage Vin at the switching point of the comparator is greater than the reference voltage Vref. As indicated above, the amount by which the input voltage Vin exceeds the reference voltage Vref at the switch point of the comparator is designated as the hysteresis voltage Vhyst.
As soon as the current through differential transistor Q6 exceeds the hysteresis current I2(h), transistors Q4 and Q3 are biased on, and transistors Q1 and Q2 are biased off. The circuit is now in positive feedback; consequently, the output voltage Vout.sup.* switches to substantially ground potential. In this state, hysteresis transistor Q3 attempts to conduct current in proportion to the current I4 through load transistor Q4. This current, referred to as the hysteresis current I3(h), can be expressed as: EQU I3(h)=I4.multidot.[(W3/L3)/(W4/L4)]
where I4 is the current through load transistor Q4, W3 and L3 represent the current path width and length dimensions of hysteresis transistor Q3, and W4 and L4 represent the current path width and length dimensions of load transistor Q4. Now, hysteresis transistor Q3 is shunting current away from load transistor Q1, as described above with respect to hysteresis transistor Q2. In this case, the input voltage Vin must fall below the reference voltage Vref by at least Vhyst before the comparator can switch back to its former state. Since hysteresis transistors Q2 and Q3 are dimensionally matched, the hysteresis voltages Vhyst above and below the reference voltage Vref are equal, as illustrated by the idealized trace of FIG. 1.
The magnitude of the hysteresis voltage Vhyst can thus be viewed as the difference between Vin and Vref at either switch point of the comparator. In MOS terminology, these voltages are designated as Von(5) for transistor Q5, and Von(6) for transistor Q6. Due to the coupling of differential transistors Q5 and Q6, the hysteresis voltage Vhyst may be defined as: EQU Vhyst=Von(5)-Von(6), or Vhyst=.DELTA.Von
The Von terms, in turn, may be defined in terms of the respective currents I5 and I6 at the switch point of the comparator, the respective transistor gain constants K5 and K6, and the respective current path dimensions WS,L5 and W6,L6. The expressions for Von(5), Von(6) and Vhyst are as follows: EQU Von(5)=[(I5.multidot.L5)/(K5.multidot.W5)].sup.1/2, EQU Von(6)=[(I6.multidot.L6)/(K6.multidot.W6)].sup.1/2, and EQU Vhyst=[(I5.multidot.L5)/(K5.multidot.W5)].sup.1/2 -[(I6.multidot.L6)/(K6.multidot.W6)].sup.1/2.
The significance of these relationships with respect to the present invention is that the gain constants K5, K6, and hence the hysteresis voltage Vhyst, are subject to variation with temperature and manufacturing process. Typically, the gain factors tend to increase nonlinearly with temperature. Variability in the manufacturing process--control of dimensions and material thickness, for example--produces circuit-to-circuit hysteresis variability. In certain applications, this may be acceptable, but in others, it is not. In applications subject to wide variation in temperature, for example, variations of 50%-75% are typically observed.
It is known, in theory, that the hysteresis variations may be mitigated by suitable adjustment of the source current Is. This may be seen in the above expression for Vhyst; for example, if K5 increases, I5 must correspondingly increase. However, known circuits for achieving the source current variation have only been marginally successful.
An example of a known compensation circuit of the type referred to above is depicted in FIG. 4. As in FIG. 3, the source current device is identified as transistor Qs. Bias transistors Q11 and Q12 are connected in series. A bias voltage Vbias developed at the junction of transistors Q11 and Q12 is applied to the gate of each transistor. The theory of operation is that the temperature and/or process variations which affect the differential transistors Q5 and Q6 of the comparator will similarly affect transistor Q11, that the corresponding variation in its gate-to-source voltage Vgs(11) will produce a compensating change in the current I11, and that a corresponding source current Is will be mirrored through the source transistor Qs.
The primary problem with this approach is that the source current Is is also influenced by the gate-to-source voltage Vgs(12) of transistor Q12 and the threshold voltage Vt(11) of transistor Q11. As a result, the source current Is developed in this manner does not sufficiently compensate for variation in the operating parameters of the differential transistors Q5 and Q6, and significant variation in the hysteresis voltage Vhyst can still occur.